`timescale 1ns / 1ps
`define illegal 2'b00
`define halfLegal 2'b01
`define legal 2'b10
`define true 1'b1
`define false 1'b0
module expr(
    input clk,
    input clr,
    input [7:0] in,
    output reg out
    );
	 reg [2:0] tem;
	 always@(posedge clk or posedge clr)begin 
		if(clr == 1)begin
			out <= `false;
			tem <= `halfLegal;
		end
		else begin
			if(clr == 1)begin
				out <= `false;
				tem <= `halfLegal;
			end
			else begin
				if(in >= "0" && in <= "9")begin
					if(tem == `halfLegal)begin
						tem <= `legal;
						out <= `true;
					end
					else begin
						tem <= `illegal;
						out <= `false;
					end
				end
				else if (in == "+" || in == "*")begin
					if(tem == `legal)begin
						tem <= `halfLegal;
						out <= `false;
					end
					else begin
						tem <= `illegal;
						out <= `false;
					end
				end
				else begin
					tem <= `illegal;
					out <= `false;
				end
			end
		end
	 end
endmodule